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| Freescale Semiconductor Data Sheet: Technical Data DSP56374 Rev. 4.2, 1/2007 DSP56374 Data Sheet 1 Overview NOTE This document contains information on a new product. Specifications and information herein are subject to change without notice. For software or simulation models (for example, IBIS files), contact sales or go to www.freescale.com. Table of Contents 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 25 Power Requirements . . . . . . . . . . . . . . . . . . . . . 26 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 27 DC Electrical Characteristics . . . . . . . . . . . . . . . 28 AC Electrical Characteristics. . . . . . . . . . . . . . . . 29 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 29 External Clock Operation . . . . . . . . . . . . . . . . . . 29 Reset, Stop, Mode Select, and Interrupt Timing . 32 Serial Host Interface SPI Protocol Timing. . . . . . 35 Serial Host Interface (SHI) I2C Protocol Timing . 41 Programming the Serial Clock . . . . . . . . . . . . . . 43 Enhanced Serial Audio Interface Timing. . . . . . . 44 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Watchdog Timer Timing . . . . . . . . . . . . . . . . . . . 53 The DSP56374 is a high-density CMOS device with 3.3 V inputs and outputs. The DSP56374 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56374 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale Semiconductor, Inc. SymphonyTM DSP family, as shown in Figure 1. Significant architectural enhancements include a barrel shifter, 24-bit addressing, and direct memory access (c) Freescale Semiconductor, Inc., 2004, 2005, 2006, 2007. All rights reserved. Overview (DMA). The DSP56374 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock. Data Sheet Conventions This data sheet uses the following conventions: OVERBAR "asserted" Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low "deasserted" Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/ Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage* VIL / VOL VIH / VOH VIH / VOH VIL / VOL Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. DSP56374 Data Sheet, Rev. 4.2 2 Freescale Semiconductor Features 5 15* 12 12* 3 Memory Expansion Area SHI Interface GPIO ESAI Interface ESAI_1 Interface Triple Timer Watch dog Timer Program RAM 6k x 24 ROM 20k x 24 X Data RAM 6k x 24 ROM 4k x 24 XM_EB Y Data RAM 6k x 24 ROM 4k x 24 YM_EB PIO_EB Peripheral Expansion Area PM_EB DDB YDB XDB PDB GDB Power Mgmt. YAB XAB PAB DAB Address Generation Unit Six Channel DMA Unit 24-Bit Bootstrap ROM DSP56300 Core Internal Data Bus Switch Clock Gen. PLL Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 x 24+5656-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter 4 JTAG OnCE XTAL EXTAL RESET PINIT/NMI MODA/IRQA/GPIO MODB/IRQB/GPIO MODC/IRQC/GPIO MODD/IRQD/GPIO * ESAI_1 and dedicated GPIO pins are not available in the 52-pin package. Figure 1. DSP56374 Block Diagram 2 2.1 * * * * Features DSP56300 Modular Chassis 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25 V Object Code Compatible with the 56K core Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter;16 bit arithmetic support Program Control with position independent code support DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 3 Features * * * * * * Six-channel DMA controller Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or 4), Output divide factor (1, 2, or 4) and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise Internal address tracing support and OnCE for Hardware/Software debugging JTAG port, supporting boundary scan, compliant to IEEE 1149.1 Very low-power CMOS design, fully static design with operating frequencies down to DC STOP and WAIT low-power standby modes 2.2 * * * * * On-chip Memory Configuration 6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM 6Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM 20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism 6Kx24 Bit Program RAM. Various memory switches are available. See memory table below. Table 1. DSP56374 Memory Switch Configurations Bit Settings MSW1 X 0 0 1 1 MSW0 X 0 1 0 1 MS 0 1 1 1 1 Prog RAM 6K 2K 4K 8K 10K Memory Sizes (24-bit words) X Data RAM 6K 10K 8K 4K 4K Y Data RAM 6K 6K 6K 6K 4K Prog ROM 20K 20K 20K 20K 20K X Data ROM 4K 4K 4K 4K 4K Y Data ROM 4K 4K 4K 4K 4K 2.3 * * Peripheral Modules Enhanced Serial Audio Interface (ESAI): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I2S, Sony, AC97, network, and other programmable protocols. Enhanced Serial Audio Interface I (ESAI_1): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I2S, Sony, AC97, network and other programmable protocols. Note: Available in the 80-pin package only. Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16, and 24-bit words. Three noise reduction filter modes. Triple Timer module (TEC) Most pins of unused peripherals may be programmed as GPIO pins. Up to 47 pins can be configured as GPIO on the 80 pin package and 20 pins on the 52 pin package. * * * DSP56374 Data Sheet, Rev. 4.2 4 Freescale Semiconductor Documentation * Hardware Watchdog Timer 2.4 Packages 80-pin and 52-pin plastic LQFP packages. 3 Documentation Table 2 lists the documents that provide a complete description of the DSP56374 and are required to design properly with the part. Documentation is available from a local Freescale Semiconductor, Inc. (formerly Motorola) distributor, semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information). Table 2. DSP56374 Documentation Document Name DSP56300 Family Manual DSP56374 User's Manual DSP56374 Technical Data Sheet DSP56374 Product Brief Description Detailed description of the 56300-family architecture and the 24-bit core processor and instruction set Detailed description of memory, peripherals, and interfaces Electrical and timing specifications; pin and package descriptions Brief description of the chip Order Number DSP56300FM/AD DSP56374UM/D DSP56374 DSP56374PB/D 4 Signal Groupings The input and output signals of the DSP56374 are organized into functional groups, which are listed in Table 3. The DSP56374 is operated from a 1.25 V and 3.3 V supply; however, some of the inputs can tolerate 5.0 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 3. DSP56374 Functional Signal Groupings Functional Group Power (VDD) Ground (GND) Scan Pins Clock and PLL Interrupt and mode control SHI ESAI ESAI_1 Port H2 Port H2 Number of Signals1 11 9 1 3 5 5 12 12 Detailed Description Table 15 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Port C4 Port E5 DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 5 Signal Groupings Table 3. DSP56374 Functional Signal Groupings (continued) Functional Group Dedicated GPIO Timer JTAG/OnCE Port Port G3 Number of Signals1 15 3 4 Detailed Description Table 12 Table 13 Table 14 Note: 1 Pins are not 5 V. tolerant unless noted. 2 Port H signals are the GPIO port signals which are multiplexed with the MOD and HREQ signals. 3 Port G signals are the dedicated GPIO port signals. 4 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. 5 Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals. 4.1 Power Table 4. Power Inputs Power Name PLLA_VDD (1) Description PLL Power-- The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND. PLLA_VDD requires a filter as shown in Figure 1 and Figure 2 below. See the DSP56374 technical data sheet for additional details. PLL Power-- The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND. PLL Power-- The voltage (1.25 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND. Core Power--The voltage (1.25 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate external decoupling capacitors. SHI, ESAI, ESAI_1, WDT and Timer I/O Power --The voltage (3.3 V) should be well-regulated, and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must provide adequate external decoupling capacitors. PLLP_VDD(1) PLLD_VDD (1) CORE_VDD (4) IO_VDD (80-pin 4) (52-pin 3) 4.2 Ground Table 5. Grounds Ground Name PLLA_GND(1) Description PLL Ground--The PLL ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND. DSP56374 Data Sheet, Rev. 4.2 6 Freescale Semiconductor Signal Groupings Table 5. Grounds (continued) Ground Name PLLP_GND(1) Description PLL Ground--The PLL ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND. PLL Ground--The PLL ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND. Core Ground--The Core ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. SHI, ESAI, ESAI_1, WDT and Timer I/O Ground--IO_GND is the ground for the SHI, ESAI, ESAI_1, WDT and Timer I/O. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. PLLD_GND(1) CORE_GND(4) IO_GND(2) 4.3 SCAN Table 6. SCAN Signals Signal Name SCAN Type State During Reset Input Signal Description Input SCAN--Manufacturing test pin. This pin must be connected to ground. 4.4 Clock and PLL Table 7. Clock and PLL Signals Signal Name EXTAL XTAL PINIT/NMI Type State during Reset Input Signal Description Input Output Input External Clock / Crystal Input--An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL. Chip Driven Crystal Output--Connects the internal Crystal Oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected. Input PLL Initial/Nonmaskable Interrupt--During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET de-assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to the internal system clock. This pin has an internal pull up resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 7 Signal Groupings 4.5 Interrupt and Mode Control Table 8. Interrupt and Mode Control Signal Name Type State during Reset MODA Input Signal Description The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is de-asserted, these inputs are hardware interrupt request lines. MODA/IRQA Input Mode Select A/External Interrupt Request A--MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is de-asserted. If the processor is in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor will exit the stop state. This pin has an internal pull up resistor. This input is 5 V tolerant. PH0 Input, output, or disconnected Input MODB Input Port H0--When the MODA/IRQA is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. Mode Select B/External Interrupt Request B--MODB/IRQB is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted. This pin has an internal pull up resistor. This input is 5 V tolerant. MODB/IRQB PH1 Input, output, or disconnected Input MODC Input Port H1--When the MODB/IRQB is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. Mode Select C/External Interrupt Request C--MODC/IRQC is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted. This pin has an internal pull up resistor. This input is 5 V tolerant. MODC/IRQC DSP56374 Data Sheet, Rev. 4.2 8 Freescale Semiconductor Signal Groupings Table 8. Interrupt and Mode Control (continued) Signal Name Type State during Reset Signal Description PH2 Input, output, or disconnected Input MODD Input Port H2--When the MODC/IRQC is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. Mode Select D/External Interrupt Request D--MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted. This pin has an internal pull up resistor. This input is 5 V tolerant. MODD/IRQD PH3 Input, output, or disconnected Input Input Port H3--When the MODD/IRQD is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. Reset--RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is de-asserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This pin has an internal pull up resistor. This input is 5 V tolerant. RESET 4.6 Serial Host Interface The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 9 Signal Groupings Table 9. Serial Host Interface Signals Signal Name SCK Signal Type Input or output State during Reset Tri-stated Signal Description SPI Serial Clock--The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock--SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected to VDD through an external pull-up resistor according to the I2C specifications. This signal is tri-stated during hardware, software, and individual reset. This pin has an internal pull up resistor. This input is 5 V tolerant. MISO Input or output Tri-stated SPI Master-In-Slave-Out--When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is de-asserted. An external pull-up resistor is not required for SPI operation. I2C Data and Acknowledge--In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VDD through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This pin has an internal pull up resistor. This input is 5 V tolerant. SCL Input or output SDA Input or open-drain output DSP56374 Data Sheet, Rev. 4.2 10 Freescale Semiconductor Signal Groupings Table 9. Serial Host Interface Signals (continued) Signal Name MOSI Signal Type Input or output State during Reset Tri-stated Signal Description SPI Master-Out-Slave-In--When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. I2C Slave Address 0--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for I2C slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This pin has an internal pull up resistor. This input is 5 V tolerant. SS Input Ignored Input SPI Slave Select--This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept de-asserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS is de-asserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. I2C Slave Address 2--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C master mode. This pin has an internal pull up resistor. This input is 5 V tolerant. HREQ Input or Output Tri-stated Host Request--This signal is an active low Schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and de-asserted at the first clock pulse of the new data word transfer. When configured for the master mode, HREQ is an input. When asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This pin can also be programmed as GPIO. PH4 Input, output, or disconnected Port H4--When HREQ is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. This pin has an internal pull up resistor. This input is 5 V tolerant. HA0 Input HA2 Input DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 11 Signal Groupings 4.7 Enhanced Serial Audio Interface Table 10. Enhanced Serial Audio Interface Signals Signal Name HCKR Signal Type Input or output State during Reset GPIO disconnected Signal Description High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. Port C2--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull up resistor. This input is 5 V tolerant. HCKT Input or output GPIO disconnected High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port C5--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull up resistor. This input is 5 V tolerant. PC2 Input, output, or disconnected PC5 Input, output, or disconnected DSP56374 Data Sheet, Rev. 4.2 12 Freescale Semiconductor Signal Groupings Table 10. Enhanced Serial Audio Interface Signals (continued) Signal Name FSR Signal Type Input or output State during Reset GPIO disconnected Signal Description Frame Sync for Receiver--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PC1 Input, output, or disconnected Port C1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. FST Input or output GPIO disconnected Frame Sync for Transmitter--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port C4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PC4 Input, output, or disconnected DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 13 Signal Groupings Table 10. Enhanced Serial Audio Interface Signals (continued) Signal Name SCKR Signal Type Input or output State during Reset GPIO disconnected Signal Description Receiver Serial Clock--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PC0 Input, output, or disconnected Port C0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SCKT Input or output GPIO disconnected Transmitter Serial Clock--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port C3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PC3 Input, output, or disconnected DSP56374 Data Sheet, Rev. 4.2 14 Freescale Semiconductor Signal Groupings Table 10. Enhanced Serial Audio Interface Signals (continued) Signal Name SDO5 Signal Type Output State during Reset GPIO disconnected Signal Description Serial Data Output 5--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port C6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO4 Output GPIO disconnected Serial Data Output 4--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port C7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO3 Output GPIO disconnected Serial Data Output 3--When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register. Serial Data Input 2--When programmed as a receiver, SDI2 is used to receive serial data into the RX2 serial receive shift register. Port C8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDI0 Input PC6 Input, output, or disconnected SDI1 Input PC7 Input, output, or disconnected SDI2 Input PC8 Input, output, or disconnected DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 15 Signal Groupings Table 10. Enhanced Serial Audio Interface Signals (continued) Signal Name SDO2 Signal Type Output State during Reset GPIO disconnected Signal Description Serial Data Output 2--When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register Serial Data Input 3--When programmed as a receiver, SDI3 is used to receive serial data into the RX3 serial receive shift register. Port C9--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO1 PC10 Output Input, output, or disconnected GPIO disconnected Serial Data Output 1--SDO1 is used to transmit data from the TX1 serial transmit shift register. Port C10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO0 PC11 Output Input, output, or disconnected GPIO disconnected Serial Data Output 0--SDO0 is used to transmit data from the TX0 serial transmit shift register. Port C11--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDI3 Input PC9 Input, output, or disconnected DSP56374 Data Sheet, Rev. 4.2 16 Freescale Semiconductor Signal Groupings 4.8 Enhanced Serial Audio Interface_1 Table 11. Enhanced Serial Audio Interface_1 Signals Signal Name HCKR_1 Signal Type Input or output State during Reset GPIO disconnected Signal Description High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI_1 receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. Port E2--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. HCKT_1 Input or output GPIO disconnected High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI_1 transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port E5--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PE2 Input, output, or disconnected PE5 Input, output, or disconnected DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 17 Signal Groupings Table 11. Enhanced Serial Audio Interface_1 Signals (continued) Signal Name FSR_1 Signal Type Input or output State during Reset GPIO disconnected Signal Description Frame Sync for Receiver_1--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR_1 pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR_1 register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR_1 register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR_1 register, synchronized by the frame sync in normal mode or the slot in network mode. PE1 Input, output, or disconnected Port E1--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant FST_1 Input or output GPIO disconnected Frame Sync for Transmitter_1--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST_1 is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI_1 transmit clock control register (TCCR_1). Port E4--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PE4 Input, output, or disconnected DSP56374 Data Sheet, Rev. 4.2 18 Freescale Semiconductor Signal Groupings Table 11. Enhanced Serial Audio Interface_1 Signals (continued) Signal Name SCKR_1 Signal Type Input or output State during Reset GPIO disconnected Signal Description Receiver Serial Clock_1--SCKR_1 provides the receiver serial bit clock for the ESAI_1. The SCKR_1 operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR_1 register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR_1 register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR_1 register, synchronized by the frame sync in normal mode or the slot in network mode. PE0 Input, output, or disconnected Port E0--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant SCKT_1 Input or output GPIO disconnected Transmitter Serial Clock_1--This signal provides the serial bit rate clock for the ESAI_1. SCKT_1 is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port E3--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant PE3 Input, output, or disconnected DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 19 Signal Groupings Table 11. Enhanced Serial Audio Interface_1 Signals (continued) Signal Name SDO5_1 Signal Type Output State during Reset GPIO disconnected Signal Description Serial Data Output 5_1--When programmed as a transmitter, SDO5_1 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0_1--When programmed as a receiver, SDI0_1 is used to receive serial data into the RX0 serial receive shift register. Port E6--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant SDO4_1 Output GPIO disconnected Serial Data Output 4_1--When programmed as a transmitter, SDO4_1 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1_1--When programmed as a receiver, SDI1_1 is used to receive serial data into the RX1 serial receive shift register. Port E7--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO3_1 Output GPIO disconnected Serial Data Output 3--When programmed as a transmitter, SDO3_1 is used to transmit data from the TX3 serial transmit shift register. Serial Data Input 2--When programmed as a receiver, SDI2_1 is used to receive serial data into the RX2 serial receive shift register. Port E8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDI0_1 Input PE6 Input, output, or disconnected SDI1_1 Input PE7 Input, output, or disconnected SDI2_1 Input PE8 Input, output, or disconnected DSP56374 Data Sheet, Rev. 4.2 20 Freescale Semiconductor Signal Groupings Table 11. Enhanced Serial Audio Interface_1 Signals (continued) Signal Name SDO2_1 Signal Type Output State during Reset GPIO disconnected Signal Description Serial Data Output 2--When programmed as a transmitter, SDO2_1 is used to transmit data from the TX2 serial transmit shift register. Serial Data Input 3--When programmed as a receiver, SDI3_1 is used to receive serial data into the RX3 serial receive shift register. Port E9--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO1_1 PE10 Output Input, output, or disconnected GPIO disconnected Serial Data Output 1--SDO1_1 is used to transmit data from the TX1 serial transmit shift register. Port E10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO0_1 PE11 Output Input, output, or disconnected GPIO disconnected Serial Data Output 0--SDO0_1 is used to transmit data from the TX0 serial transmit shift register. Port E11--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDI3_1 Input PE9 Input, output, or disconnected DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 21 Signal Groupings 4.9 Dedicated GPIO-Port G Table 12. Dedicated GPIO-Port G Signals Signal Name PG0 Type Input, output, or disconnected State During Reset GPIO disconnected Signal Description Port G0--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG1 Input, output, or disconnected GPIO disconnected Port G1--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG2 Input, output, or disconnected GPIO disconnected Port G2--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG3 Input, output, or disconnected GPIO disconnected Port G3--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG4 Input, output, or disconnected GPIO disconnected Port G4--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG5 Input, output, or disconnected GPIO disconnected Port G5--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG6 Input, output, or disconnected GPIO disconnected Port G6--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG7 Input, output, or disconnected GPIO disconnected Port G7--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG8 Input, output, or disconnected GPIO disconnected Port G8--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant DSP56374 Data Sheet, Rev. 4.2 22 Freescale Semiconductor Signal Groupings Table 12. Dedicated GPIO-Port G Signals (continued) Signal Name PG9 Type Input, output, or disconnected State During Reset GPIO disconnected Signal Description Port G9--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG10 Input, output, or disconnected GPIO disconnected Port G10--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG11 Input, output, or disconnected GPIO disconnected Port G11--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG12 Input, output, or disconnected GPIO disconnected Port G12--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG13 Input, output, or disconnected GPIO disconnected Port G13--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG14 Input, output, or disconnected GPIO disconnected Port G14--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 23 Signal Groupings 4.10 Timer Table 13. Timer Signal Signal Name TIO0 Type State during Reset Signal Description Input or Output GPIO Input Timer 0 Schmitt-Trigger Input/Output--When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/status register (TCSR0). If TIO0 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input. Internal Pull down resistor. This input is 5 V tolerant TIO1 Input or Output Watchdog Timer Output Timer 1 Schmitt-Trigger Input/Output--When timer 1 functions as an external event counter or in measurement mode, TIO1 is used as input. When timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 1control/status register (TCSR1). If TIO1 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input. WDT Output WDT--When this pin is configured as a hardware watchdog timer pin, this signal is asserted low when the hardware watchdog timer counts down to zero. Internal Pull down resistor. This input is 5 V tolerant TIO2 Input or Output PLOCK Output Timer 2 Schmitt-Trigger Input/Output--When timer 2 functions as an external event counter or in measurement mode, TIO2 is used as input. When timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer control/status register (TCSR2). If TIO2 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input . DSP56374 Data Sheet, Rev. 4.2 24 Freescale Semiconductor Maximum Ratings Table 13. Timer Signal (continued) Signal Name PLOCK Type State during Reset Signal Description Output PLOCK--When this pin is configured as a PLL lock pin, this signal is asserted high when the on-chip PLL enabled and locked and de-asserted when the PLL enabled and unlocked. This pin is also asserted high when the PLL is disabled. Internal Pull down resistor. This input is 5 V tolerant 4.11 JTAG/OnCE Interface Table 14. JTAG/OnCE Interface Signal Name TCK Signal Type Input State during Reset Input Signal Description Test Clock--TCK is a test clock input signal used to synchronize the JTAG test logic. Internal Pull up resistor. This input is 5 V tolerant. TDI Input Input Test Data Input--TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK. Internal Pull up resistor. This input is 5 V tolerant. TDO Output Tri-stated Test Data Output--TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Test Mode Select--TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK. Internal Pull up resistor. This input is 5 V tolerant. TMS Input Input 5 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either GND or VDD). The suggested value for a pullup or pulldown resistor is 4.7 k. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 25 Power Requirements NOTE In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 15. Maximum Ratings Rating1 Supply Voltage Symbol VCORE_VDD, VPLLD_VDD VPLLP_VDD, VIO_VDD, VPLLA_VDD, Maximum CORE_VDD power supply ramp time4 All "5.0V tolerant" input voltages Current drain per pin excluding VDD and GND(Except for pads listed below) SCK_SCL TDO Operating temperature Storage temperature ESD protected voltage (Human Body Model) ESD protected voltage (Machine Model) range3 Tr VIN I ISCK IJTAG TJ TSTG Value1, 2 Unit V -0.3 to + 1.6 -0.3 to + 4.0 10 GND - 0.3 to 6V 12 16 24 80 LQFP = 105 52 LQFP = 110 V ms V mA mA ma C C V V -55 to +125 2000 200 Note: 1 GND = 0 V, T = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50pF J 2 Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3 Operating temperature qualified for automotive applications. T = T + x Power. Variables used were J A JA Core Current = 100 mA, I/O Current = 60 mA, Core Voltage = 1.3 V, I/O Voltage = 3.46 V, TA = 85C 4 If the power supply ramp to full supply time is longer than 10 ms, the POR circuitry will not operate correctly, causing erroneous operation. 6 Power Requirements To prevent high current conditions due to possible improper sequencing of the power supplies, the connection shown below is recommended to be made between the DSP56374 IO_VDD and Core_VDD power pins. DSP56374 Data Sheet, Rev. 4.2 26 Freescale Semiconductor Thermal Characteristics IO_VDD External Schottky Diode Core_VDD To prevent a high current condition upon power up, the IO_VDD must be applied ahead of the Core_VDD as shown below if the external Schottky is not used. Core_VDD IO_VDD For correct operation of the internal power on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms. This is shown below. Tr 1.25 V 0V Core_VDD 7 Thermal Characteristics Table 16. Thermal Characteristics Characteristic Natural Convection, Junction-to-ambient thermal resistance1,2 Junction-to-case thermal resistance3 Symbol RJA or JA RJC or JC LQFP Values 68 (52 LQFP) 50 (80 LQFP) 17 (52 LQFP) 11 (80 LQFP) Unit C/W C/W Note: 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 27 DC Electrical Characteristics 8 DC Electrical Characteristics Table 17. DC Electrical Characteristics Characteristics Supply voltages * Core (Core_VDD) * PLL (PLLD_VDD) Supply voltages * I/O (IO_VDD) * PLL (PLLP_VDD) * PLL (PLLA_VDD) Input high voltage * All pins Symbol VDD Min 1.2 Typ 1.25 Max 1.3 Unit V VDDIO 3.14 3.3 3.46 V V VIH 2.0 -- VIO_VDD+2V Note: All 3.3-V supplies must rise prior to the rise of the 1.25-V supplies to avoid a high current condition and possible system damage. Input low voltage * All pins Input leakage current Clock pin Input Capacitance (EXTAL) High impedance (off-state) input current (@ 3.46V) Output high voltage * IOH = -5 mA * XTAL Pin IOH = -10mA Output low voltage * IOL = 5 mA * XTAL Pin IOL = 10 mA Internal supply current1 (core only) at internal clock of 150 MHz * In Normal mode * In Wait mode * In Stop mode2 VIL IIN CIN ITSI VOH -10 2.4 -0.3 -- -- -- 4.7 -- -- 84 -- 0.8 84 V A pF A V VOL -- -- 0.4 V ICCI ICCW ICCS CIN -- -- -- -- 65 16 1.2 -- 100 -- -- 10 mA mA mA pF Input capacitance Note: 1 The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCORE_VDD = 1.25V, VDD_IO = 3.3V at TJ = 25C. Maximum internal supply current is measured with VCORE_VDD = 1.30V, VIO_VDD) = 3.46V at TJ = 115C. 2 In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float). DSP56374 Data Sheet, Rev. 4.2 28 Freescale Semiconductor AC Electrical Characteristics 9 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.8 V and a VIH minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56374 output levels are measured with the production test machine VOL and VOH reference levels set at 1.0 V and 1.8 V, respectively. 10 No. 1 2 3 Internal Clocks Table 18. INTERNAL CLOCKS1 Characteristics Comparison Frequency Input Clock Frequency Output clock Frequency (with PLL enabled) 2,3 Symbol Fref FIN FOUT Tc 75 13.3 -- 40 Ef 50 150 60 Min 5 Typ -- Fref*NR (Ef x MF x FM)/ (PDF x DF x OD) 150 MHz ns MHz % -- FVCO=300MHz~600MHz Max 20 Unit MHz Condition Fref = FIN/NR NR is input divider value FOUT=FVCO/NO where NO is output divider value 4 5 Output clock Frequency (with PLL disabled) 2,3 Duty Cycle FOUT -- Note: 1 See users manual for definition. 2 DF = Division Factor Ef = External Frequency Mf = Multiplication Factor PDF = Predivision Factor FM= Frequency Multiplier OD = Output Divider Tc = Internal Clock Period 3 Maximum frequency will vary depending on the ordered part number. 11 External Clock Operation The DSP56374 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; an example is shown below. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 29 External Clock Operation Suggested component values: f osc = 24.576 MHz R = 1 M 10% C (EXTAL)= 18 pF C (XTAL) = 47 pF Calculations are for a 12 - 49 MHz crystal with the following parameters: * shunt capacitance (C0) of 10 pF - 12 pF * series resistance 40 Ohm * drive level of 10 W If the DSP56374 system clock is an externally supplied square wave voltage source, it is connected to EXTAL (Figure 2.). When the external square wave source connects to EXTAL, the XTAL pin is not used. VIH EXTAL VIL ETH 6 8 ETL 7 ETC Midpoint Note: The midpoint is 0.5 (VIH + VIL). Figure 2. External Clock Timing Table 19. Clock Operation No. 6 Characteristics EXTAL input high EXTAL input low2 (40% to 60% duty cycle) 8 EXTAL cycle time * With PLL disabled * With PLL enabled 9 Instruction cycle time= ICYC = TC3 * With PLL disabled * With PLL enabled Icyc 6.67 6.67 inf 13.33 ns Etc 6.67 50 inf 200 ns 1 Symbol Eth Min 3.33 Max 50 Units ns (40% to 60% duty cycle) 7 Etl 3.33 50 ns DSP56374 Data Sheet, Rev. 4.2 30 Freescale Semiconductor External Clock Operation Table 19. Clock Operation (continued) No. Characteristics Symbol Min Max Units Note: 1 Measured at 50% of the input transition. 2 The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. 3 A valid clock signal must be applied to the EXTAL pin within 3 ms of the DSP56374 being powered up. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 31 Reset, Stop, Mode Select, and Interrupt Timing 12 No. 10 11 Reset, Stop, Mode Select, and Interrupt Timing Table 20. Reset, Stop, Mode Select, and Interrupt Timing Characteristics Delay from RESET assertion to all pins at reset value3 Required RESET duration4 * Power on, external clock generator, PLL disabled * Power on, external clock generator, PLL enabled 2 xTC 2 x TC 13.4 13.4 -- -- ns ns Expression -- Min -- Max 11 Unit ns 13 Syn reset deassert delay time * Minimum * Maximum (PLL enabled) 2x TC (2xTC)+TLOCK 13.4 5.0 10.0 10.0 2 xTC 2 xTC 10 x TC + 5 13.4 13.4 72 -- -- -- -- -- -- -- ns ms ns ns ns ns ns 14 15 16 17 18 19 Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from interrupt trigger to interrupt code execution Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)1, 2, 3 * PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0) * PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) 9+(128x TC) 854 -- s 25x TC 165 -- ns 9+(128xTC) + TLOCK (25 x TC) + TLOCK 10 x TC + 3.0 5.7 5 69.0 ms ms ns 20 * Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution1 DSP56374 Data Sheet, Rev. 4.2 32 Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing Table 20. Reset, Stop, Mode Select, and Interrupt Timing (continued) No. 21 Characteristics Interrupt Requests Rate1 * ESAI, ESAI_1, SHI, Timer * DMA * IRQ, NMI (edge trigger) * IRQ (level trigger) 22 DMA Requests Rate * Data read from ESAI, ESAI_1, SHI * Data write to ESAI, ESAI_1, SHI * Timer * IRQ, NMI (edge trigger) 6 x TC 7 x TC 2 x TC 3 x TC -- -- -- -- 40.0 46.7 13.4 20.0 ns ns ns ns 12 x TC 8 x TC 8 x TC 12 x TC -- -- -- -- 80.0 53.0 53.0 80.0 ns ns ns ns Expression Min Max Unit Note: 1 When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. 2 For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by the OMR Bit 6 settings. For PLL enable, (if bet 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0.5 ms. 3 4 Periodically sampled and not 100% tested. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and valid. When the VDD is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. VIH RESET 11 10 All Pins Reset Value 13 Figure 3. Reset Timing DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 33 Reset, Stop, Mode Select, and Interrupt Timing IRQA, IRQB, IRQC, IRQD, NMI 19 18 a) First Interrupt Instruction Execution General Purpose I/O 20 IRQA, IRQB, IRQC, IRQD, NMI b) General Purpose I/O Figure 4. External Fast Interrupt Timing IRQA, IRQB, IRQC, IRQD, NMI 16 IRQA, IRQB, IRQC, IRQD, NMI 17 Figure 5. External Interrupt Timing (Negative Edge-Triggered) RESET VIH 14 15 MODA, MODB, MODC, MODD, PINIT VIH VIL VIH VIL IRQA, IRQB, IRQC,IRQD, NMI Figure 6. Recovery from Stop State Using IRQA Interrupt Service DSP56374 Data Sheet, Rev. 4.2 34 Freescale Semiconductor Serial Host Interface SPI Protocol Timing 13 No. 23 Serial Host Interface SPI Protocol Timing Table 21. Serial Host Interface SPI Protocol Timing Characteristics1,3,4 Minimum serial clock cycle = tSPICC(min) Mode Master/Slave Filter Mode Bypassed Very Narrow Narrow Wide Expression 10.0 x TC + 9 10.0 x TC + 9 10.0 x TC + 133 10.0 x TC + 333 -- -- -- -- -- -- -- -- 2.0 x TC + 19.6 2.0 x TC + 19.6 2.0 x TC + 86.6 2.0 x TC + 186.6 -- -- -- -- 2.0 x TC + 19.6 2.0 x TC + 19.6 2.0 x TC + 86.6 2.0 x TC + 186.6 -- -- -- Min 76.0 76.0 200.0 400.0 -- -- -- -- 38.0 38.0 100.0 200.0 33.0 33.0 100.0 200.0 38.0 38.0 100.0 200.0 33.0 33.0 100.0 200.0 -- -- Max -- -- -- -- 0 10 50 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns XX Tolerable Spike width on data or clock in. -- Bypassed Very Narrow Narrow Wide 24 Serial clock high period Master Bypassed Very Narrow Narrow Wide Slave Bypassed Very Narrow Narrow Wide 25 Serial clock low period Master Bypassed Very Narrow Narrow Wide Slave Bypassed Very Narrow Narrow Wide 26 Serial clock rise/fall time Master Slave -- -- DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 35 Serial Host Interface SPI Protocol Timing Table 21. Serial Host Interface SPI Protocol Timing (continued) No. 27 Characteristics1,3,4 SS assertion to first SCK edge CPHA = 0 Mode Slave Filter Mode Bypassed Very Narrow Narrow Wide CPHA = 1 Slave Bypassed Very Narrow Narrow Wide 28 Last SCK edge to SS not asserted Slave Bypassed Very Narrow Narrow Wide 29 Data input valid to SCK edge (data input set-up time) Master /Slave Bypassed Very Narrow Narrow Wide 30 SCK last sampling edge to data input not valid Master /Slave Bypassed Very Narrow Narrow Wide 31 32 33 SS assertion to data out active SS deassertion to data high impedance2 SCK edge to data out valid (data out delay time) Slave Slave Master /Slave -- -- Bypassed Very Narrow Narrow Wide 34 SCK edge to data out not valid (data out hold time) Master /Slave Bypassed Very Narrow Narrow Wide 35 SS assertion to data out valid (CPHA = 0) Slave -- Expression 2.0 x TC + 12.6 2.0 x TC + 2.6 2.0 x TC - 37.45 2.0 x TC - 87.45 -- -- -- -- -- -- -- -- -- -- -- -- 3.0 x TC 3.0 x TC + 23.2 3.0 x TC + 53.2 3.0 x TC + 80 -- -- 3.0 x TC + 26.1 3.0 x TC + 90.4 3.0 x TC + 116.4 3.0 x TC + 203.4 2.0 x TC 2.0 x TC + 1.6 2.0 x TC + 41.6 2.0 x TC + 91.6 -- Min 26 16 0 0 10 0 0 0 12 22 100 200 0 0 0 0 20 43.2 73.2 100.0 5 -- -- -- -- -- 13.4 15 55 105 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9 46.2 110.4 136.4 223.4 -- -- -- -- 12.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DSP56374 Data Sheet, Rev. 4.2 36 Freescale Semiconductor Serial Host Interface SPI Protocol Timing Table 21. Serial Host Interface SPI Protocol Timing (continued) No. 36 Characteristics1,3,4 SCK edge following the first SCK sampling edge to HREQ output deassertion Mode Slave Filter Mode Bypassed Very Narrow Narrow Wide 37 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Slave Bypassed Very Narrow Narrow Wide 38 39 40 SS deassertion to HREQ output not deasserted (CPHA = 0) SS deassertion pulse width (CPHA = 0) HREQ in assertion to first SCK edge Slave Slave Master -- -- Bypassed Very Narrow Narrow Wide 41 HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) First SCK edge to HREQ in not asserted (HREQ in hold time) HREQ assertion width Master -- Expression 3.0 x TC + 30 3.0 x TC + 40 3.0 x TC + 80 3.0 x TC + 120 4.0 x TC 4.0 x TC 4.0 x TC 4.0 x TC 3.0 x TC + 30 2.0 x TC 0.5 x TSPICC + 3.0 x TC + 5 0.5 x TSPICC + 3.0 x TC + 5 0.5 x TSPICC + 3.0 x TC + 5 0.5 x TSPICC + 3.0 x TC + 5 -- Min 50 60 100 150 57.0 67.0 107.0 157.0 50.0 13.4 63 63 125 225 0 Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 42 43 Master Master -- -- -- 3.0 x TC 0 20 -- -- ns ns Note: 1V CORE_VDD = 1.2 5 0.05 V; TJ = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50 pF 2 Periodically sampled, not 100% tested 3 All times assume noise free inputs. 4 All times assume internal clock frequency of 150 MHz. 5 Equation applies when the result is positive T . C DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 37 Serial Host Interface SPI Protocol Timing SS (Input) 25 24 SCK (CPOL = 0) (Output) 24 25 SCK (CPOL = 1) (Output) 29 30 MISO (Input) MSB Valid 33 MOSI (Output) 40 42 HREQ (Input) 43 MSB 29 LSB Valid 34 LSB 30 23 26 26 26 23 26 Figure 7. SPI Master Timing (CPHA = 0) DSP56374 Data Sheet, Rev. 4.2 38 Freescale Semiconductor Serial Host Interface SPI Protocol Timing SS (Input) 25 24 SCK (CPOL = 0) (Output) 24 25 SCK (CPOL = 1) (Output) 29 30 MISO (Input) MSB Valid 33 MOSI (Output) 40 42 HREQ (Input) 43 MSB 41 LSB Valid 34 LSB 29 30 26 23 26 26 23 26 Figure 8. SPI Master Timing (CPHA = 1) DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 39 Serial Host Interface SPI Protocol Timing SS (Input) 25 24 SCK (CPOL = 0) (Input) 27 24 25 SCK (CPOL = 1) (Input) 35 31 MISO (Output) 29 30 MOSI (Input) MSB Valid 36 HREQ (Output) LSB Valid 38 34 MSB 29 30 33 34 LSB 32 23 26 26 26 23 26 39 28 Figure 9. SPI Slave Timing (CPHA = 0) DSP56374 Data Sheet, Rev. 4.2 40 Freescale Semiconductor Serial Host Interface (SHI) I2C Protocol Timing SS (Input) 25 24 SCK (CPOL = 0) (Input) 27 24 25 SCK (CPOL = 1) (Input) 33 31 MISO (Output) 29 30 MOSI (Input) MSB Valid 36 HREQ (Output) LSB Valid 37 MSB 29 30 33 34 32 LSB 26 26 26 23 26 28 Figure 10. SPI Slave Timing (CPHA = 1) 14 Serial Host Interface (SHI) I2C Protocol Timing Table 22. SHI I2C Protocol Timing Standard I2C No. XX Characteristics1,2,3,4,5 Tolerable Spike Width on SCL or SDA Filters Bypassed Very Narrow Filters enabled Narrow Filters enabled Wide Fileters enabled. 44 44 45 46 SCL clock frequency SCL clock cycle Bus free time Start condition set-up time FSCL TSCL TBUF TSUSTA Symbol/ Expression -- -- -- -- -- -- 10 4.7 4.7 0 10 50 100 100 -- -- -- -- -- -- -- -- 2.5 1.3 0.6 0 10 50 100 400 -- -- -- ns ns ns ns kHz s s s Standard Min Max Fast-Mode Min Max Unit DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 41 Serial Host Interface (SHI) I2C Protocol Timing Table 22. SHI I2C Protocol Timing (continued) Standard I2C No. 47 48 49 50 51 52 53 54 Characteristics1,2,3,4,5 Start condition hold time SCL low period SCL high period SCL and SDA rise time SCL and SDA fall time Data set-up time Data hold time DSP clock frequency * Filters bypassed * Very Narrrow filters enabled * Narrow filters enabled * Wide filters enabled 55 56 57 58 SCL low to data out valid Stop condition setup time HREQ in deassertion to last SCL edge (HREQ in set-up time) First SCL sampling edge to HREQ output deassertion2 * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled 59 Last SCL edge to HREQ output not deasserted2 * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled 60 HREQ in assertion to first SCL edge * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled 61 First SCL edge to HREQ is not asserted (HREQ in hold time.) tHO;RQI TVD;DAT TSU;STO tSU;RQI TNG;RQO 4 x TC + 30 4 x TC + 50 -- -- -- -- 57.0 77.0 157.0 257.0 -- -- -- -- 57.0 67.0 157.0 257.0 ns ns ns ns Symbol/ Expression THD;STA TLOW THIGH TR TF TSU;DAT THD;DAT FOSC 10.6 10.6 11.8 13.1 -- 4.0 0.0 -- -- -- -- 3.4 -- -- 28.5 28.5 39.7 61.0 -- 0.6 0.0 -- -- -- -- 0.9 -- -- MHz MHz MHz MHz s s ns Standard Min 4.0 4.7 4.0 -- -- 250 0.0 Max -- -- -- 5.0 5.0 -- -- Fast-Mode Min 0.6 1.3 1.3 -- -- 100 0.0 Max -- -- -- 5.0 5.0 -- 0.9 s s s ns ns ns s Unit 4 x TC + 130 4 x TC + 230 TAS;RQO 2 x TC + 30 2 x TC + 40 44 54 94 144 -- -- -- -- 44 54 94 144 -- -- -- -- ns ns ns ns 2 x TC + 80 2 x TC + 130 TAS;RQI 4327 4317 4282 4227 0.0 -- -- -- -- -- 927 917 877 827 0.0 -- -- -- -- -- ns ns ns ns ns DSP56374 Data Sheet, Rev. 4.2 42 Freescale Semiconductor Programming the Serial Clock Table 22. SHI I2C Protocol Timing (continued) Standard I2C No. Characteristics1,2,3,4,5 Symbol/ Expression Standard Min Max Fast-Mode Min Max Unit Note: 1 VCORE_VDD = 1.2 5 0.05 V; TJ = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50 pF 2 Pull-up resistor: R P (min) = 1.5 kOhm 3 Capacitive load: C b (max) = 50 pF 4 All times assume noise free inputs 5 All times assume internal clock frequency of 150MHz 15 Programming the Serial Clock 2 2 The programmed serial clock cycle, T I CCP, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock control register). The expression for T I CCP is T I2CCP = [TC x 2 x (HDM[7:0] + 1) x (7 x (1 - HRS) + 1)] Eqn. 1 where -- HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed. -- HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected. In I2C mode, the user may select a value for the programmed serial clock cycle from 6 x TC (if HDM[7:0] = $02 and HRS = 1) Eqn. 2 to 4096 x TC (if HDM[7:0] = $FF and HRS = 0) 2 Eqn. 3 The programmed serial clock cycle (TI CCP ) should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as shown in Table 23. Table 23. SCL Serial Clock Cycle (TSCL) Generated as Master Nominal TI2CCP + 3 x TC + 45ns + TR DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 43 Enhanced Serial Audio Interface Timing 44 46 SCL 50 45 52 SDA Stop Start 47 61 60 HREQ MSB 58 57 59 LSB 55 ACK 56 Stop 51 53 49 48 Figure 11. I2C Timing 16 No. 62 Enhanced Serial Audio Interface Timing Table 24. Enhanced Serial Audio Interface Timing Characteristics1, 2, 3 Clock cycle5 Symbol tSSICC tSSICCH 2 x Tc - 0.5 2 x Tc tSSICCL 2 x Tc 2 x Tc -- -- 13.4 13.4 -- -- -- -- 17.0 7.0 17.0 7.0 19.0 9.0 19.0 9.0 16.0 6.0 x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a ns ns ns ns ns 12.8 13.4 -- -- ns Expression3 4 x Tc 4 x Tc Min 26.4 26.4 Max -- -- Condition4 x ck i ck ns Unit ns 63 Clock high period * For internal clock * For external clock 64 Clock low period * For internal clock * For external clock 65 SCKR edge to FSR out (bl) high 66 SCKR edge to FSR out (bl) low 6 -- -- -- -- 67 SCKR edge to FSR out (wr) high -- -- -- -- 68 SCKR edge to FSR out (wr) low6 -- -- -- -- 69 SCKR edge to FSR out (wl) high -- -- -- -- DSP56374 Data Sheet, Rev. 4.2 44 Freescale Semiconductor Enhanced Serial Audio Interface Timing Table 24. Enhanced Serial Audio Interface Timing (continued) No. 70 Characteristics1, 2, 3 SCKR edge to FSR out (wl) low Symbol -- Expression3 -- Min -- -- 71 Data in setup time before SCKR (SCK in synchronous mode) edge Data in hold time after SCKR edge FSR input (bl, wr) high before SCKR edge 6 -- -- 12.0 19.0 -- -- 3.5 9.0 73 -- -- 2.0 12.0 74 FSR input (wl) high before SCKR edge -- -- 2.0 12.0 75 FSR input hold time after SCKR edge -- -- 2.5 8.5 76 Flags input setup before SCKR edge -- -- 0.0 19.0 77 Flags input hold time after SCKR edge -- -- 6.0 0.0 78 SCKT edge to FST out (bl) high -- -- -- -- 79 SCKT edge to FST out (bl) low SCKT edge to FST out (wr) high6 6 Max 17.0 7.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18.0 8.0 20.0 10.0 20.0 10.0 22.0 12.0 19.0 9.0 20.0 10.0 22.0 17.0 17.0 11.0 18.0 13.0 21.0 16.0 Condition4 x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck Unit ns ns 72 ns ns ns ns ns ns ns -- -- -- -- ns 80 -- -- -- -- ns 81 SCKT edge to FST out (wr) low -- -- -- -- ns 82 SCKT edge to FST out (wl) high -- -- -- -- ns 83 SCKT edge to FST out (wl) low -- -- -- -- ns 84 SCKT edge to data out enable from high impedance SCKT edge to transmitter #0 drive enable assertion SCKT edge to data out valid 7 -- -- -- -- ns 85 -- -- -- -- ns 86 -- -- -- -- ns 87 SCKT edge to data out high impedance -- -- -- -- ns DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 45 Enhanced Serial Audio Interface Timing Table 24. Enhanced Serial Audio Interface Timing (continued) No. 88 Characteristics1, 2, 3 SCKT edge to transmitter #0 drive enable deassertion7 FST input (bl, wr) setup time before SCKT edge6 FST input (wl) setup time before SCKT edge FST input hold time after SCKT edge Symbol -- Expression3 -- Min -- -- -- -- 2.0 18.0 -- -- 2.0 18.0 -- -- 4.0 5.0 92 93 94 FST input (wl) to data out enable from high impedance FST input (wl) to transmitter #0 drive enable assertion Flag output valid after SCKT rising edge -- -- -- -- -- -- -- -- -- -- 95 96 97 HCKR/HCKT clock cycle HCKT input edge to SCKT output HCKR input edge to SCKR output -- -- -- 2 x TC -- -- 13.4 -- -- Max 14.0 9.0 -- -- -- -- -- -- 21.0 14.0 14.0 9.0 -- 18.0 18.0 Condition4 x ck i ck x ck i ck x ck i ck x ck i ck -- -- x ck i ck ns ns ns ns ns ns ns ns ns Unit ns 89 90 91 Note: 1V CORE_VDD = 1.25 0.05 V; TJ = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50 pF 2 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that SCKT and SCKR are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that SCKT and SCKR are the same clock) 3 bl = bit length wl = word length wr = word length relative 4 SCKT(SCKT pin) = transmit clock SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock 5 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. 6 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7 Periodically sampled and not 100% tested. 8 ESAI_1 specs match those of ESAI. DSP56374 Data Sheet, Rev. 4.2 46 Freescale Semiconductor Enhanced Serial Audio Interface Timing 62 SCKT (Input/Output) 63 64 78 79 FST (Bit) Out 83 FST (Word) Out 87 85 Data Out 92 Transmitter #0 Drive Enable 90 94 FST (Bit) In 91 93 FST (Word) In 95 Flags Out Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. Figure 12 is drawn assuming positive polarity bit clock (TCKP=0) and positive frame sync polarity (TFSP=0). 94 86 89 First Bit Last Bit 87 88 84 See Note Figure 12. ESAI Transmitter Timing DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 47 Enhanced Serial Audio Interface Timing 62 63 SCKR (Input/Output) 65 FSR (Bit) Out 69 FSR (Word) Out 72 71 Data In 73 FSR (Bit) In 74 FSR (Word) In 75 75 First Bit Last Bit 70 64 66 76 77 Flags In Note: Figure 13 is drawn assuming positive polarity bit clock (RCKP=0) and positive frame sync polarity (RFSP=0). Figure 13. ESAI Receiver Timing DSP56374 Data Sheet, Rev. 4.2 48 Freescale Semiconductor Timer Timing HCKT SCKT (output) 95 96 Note: Figure 14 is drawn assuming positive polarity high frequency clock (THCKP=0) and positive bit clock polarity (TCKP=0). Figure 14. ESAI HCKT Timing HCKR SCKR (output) 95 97 Note: Figure 15 is drawn assuming positive polarity high frequency clock (RHCKP=0) and positive bit clock polarity (RCKP=0). Figure 15. ESAI HCKR Timing 17 Timer Timing Table 25. Timer Timing 150 MHz No. 98 99 TIO Low TIO High Characteristics Expression Min 2 x TC + 2.0 2 x TC + 2.0 15.4 15.4 Max -- -- ns ns Unit Note: VCORE_VDD = 1.25 V 0.05 V; TJ = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50 pF TIO 98 99 Figure 16. TIO Timer Event Input Restrictions DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 49 GPIO Timing 18 No. GPIO Timing Table 26. GPIO Timing Characteristics1 EXTAL edge to GPIO out valid (GPIO out delay time)2 EXTAL edge to GPIO out not valid (GPIO out hold time) GPIO In valid to EXTAL edge (GPIO in set-up time)2 EXTAL edge to GPIO in not valid (GPIO in hold time) Minimum GPIO pulse high width Minimum GPIO pulse low width GPIO out rise time GPIO out fall time 2 2 Expression Min -- -- 2 0 Max 7 7 -- -- -- -- 13.0 13.0 Unit ns ns ns ns ns ns ns ns 100 101 102 103 104 105 106 107 TC + 13 TC + 13 -- -- 19.7 19.7 -- -- Note: 1V CORE_VDD = 1.25 V 0.05 V; TJ = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50 pF 2 PLL Disabled, EXTAL driven by a square wave. EXTAL 100 101 GPIO (Output) 102 GPIO (Input) GPIO (Output) 104 106 105 107 Valid 103 Figure 17. GPIO Timing 19 JTAG Timing Table 27. JTAG Timing All frequencies No. 108 Characteristics Min TCK frequency of operation (1/(TC x 3); maximum 10 MHz) -- Max 10.0 MHz Unit DSP56374 Data Sheet, Rev. 4.2 50 Freescale Semiconductor JTAG Timing Table 27. JTAG Timing (continued) All frequencies No. 109 110 111 112 113 114 115 116 117 118 119 Note: 1. VCORE_VDD = 1.25 V 0.05 V; TJ = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50 pF 2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. Characteristics Min TCK cycle time in Crystal mode TCK clock pulse width measured at 1.65 V TCK rise and fall times Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance 100.0 50.0 -- 15.0 24.0 -- -- 5.0 25.0 -- -- Max -- -- 3.0 -- -- 40.0 40.0 -- -- 44.0 44.0 Unit ns ns ns ns ns ns ns ns ns ns ns 109 110 TCK (Input) VIH 111 VM VIL 111 110 VM Figure 18. Test Clock Input Timing Diagram DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 51 JTAG Timing TCK (Input) VIH VIL 112 113 Data Inputs 114 Data Outputs 115 Data Outputs 114 Data Outputs Input Data Valid Output Data Valid Output Data Valid Figure 19. Debugger Port Timing Diagram TCK (Input) TDI TMS (Input) VIH VIL 116 Input Data Valid 118 117 TDO (Output) 119 TDO (Output) 118 TDO (Output) Output Data Valid Output Data Valid Figure 20. Test Access Port Timing Diagram DSP56374 Data Sheet, Rev. 4.2 52 Freescale Semiconductor Watchdog Timer Timing 20 No. 120 121 Watchdog Timer Timing Table 28. Watchdog Timer Timing Characteristics Delay from time-out to fall of TIO1 Delay from timer clear to rise of TIO1 Expression 2 x Tc 2 x Tc Min 13.4 13.4 Max -- -- Unit ns ns DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 53 Watchdog Timer Timing Appendix A Package Information A.1 DSP56374 Pinout HCKR_1_PE2 SCKR_1_PE0 FST_PC4 HCKT_1_PE5 GPIO_PG14 FST_1_PE4 SCKT_1_PE3 FSR_1_PE1 HCKR_PC2 SCKR_PC0 HCKT_PC5 SDO5_PC6 SDO4_PC7 Core_Gnd Core_Vdd FSR_PC1 IO_Gnd SCKT_PC3 77 69 62 68 80 79 78 76 74 73 72 71 70 IO_Vdd MODA_IRQA_PH0 MODB_IRQB_PH1 GPIO_PG13 GPIO_PG12 MODC_IRQC_PH2 MODD_IRQD_PH3 GPIO_PG11 Core_Vdd Core_Gnd GPIO_PG10 GPIO_PG9 HREQ_PH4 SS_HA2 SCK_SCL MISO_SDA MOSI_HA0 GPIO_PG8 GPIO_PG7 IO_Gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 75 67 66 65 64 63 IO_Vdd SCAN SDO5_1_PE6 SDO4_1_PE7 SDO3_PC8 SDO2_PC9 SDO1_PC10 SDO0_PC11 SDO3_1_PE8 SDO2_1_PE9 Core_Vdd Core_Gnd SDO1_1_PE10 SDO0_1_PE11 PINIT_NMI IO_Vdd XTAL EXTAL PLLD_Vdd PLLD_Gnd PLLP_Gnd PLLP_Vdd 22 23 28 34 36 37 24 25 26 27 31 21 32 29 30 33 35 38 PLOCK/TIO2 GPIO_PG6 GPIO_PG5 GPIO_PG4 GPIO_PG3 GPIO_PG2 GPIO_PG1 GPIO_PG0 39 PLLA_Vdd PLLA_Gnd WDT/TIO1 Core_Gnd RESET_B Core_Vdd IO_Vdd TIO00 TDO TMS TCK TDI 40 1.25 V Filter 3.3 V Figure A-1. 80-Pin Vdd Connections DSP56374 Data Sheet, Rev. 4.2 54 Freescale Semiconductor Watchdog Timer Timing HCKR_PC2 SCKR_PC0 Core_Vdd HCKT_PC5 SDO5_PC6 SDO4_PC7 Core_Gnd FSR_PC1 FST_PC4 IO_Gnd SCKT_PC3 45 41 44 52 51 50 49 48 46 47 IO_Vdd MODA_IRQA_PH0 MODB_IRQB_PH1 MODC_IRQC_PH2 MODD_IRQD_PH3 Core_Vdd Core_Gnd HREQ_PH4 SS_HA2 SCK_SCL MISO_SDA MOSI_HA0 IO_Gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 40 43 42 IO_Vdd SCAN 39 38 37 36 35 34 33 32 31 30 29 28 27 SDO3_PC8 SDO2_PC9 SDO1_PC10 SDO0_PC11 Core_Vdd Core_Gnd PINIT_NMI XTAL EXTAL PLLD_Vdd PLLD_Gnd PLLP_Gnd PLLP_Vdd 19 15 17 16 18 20 21 22 23 24 14 25 PLLA_Vdd PLOCK/TIO2 PLLA_Gnd WDT/TIO1 Core_Gnd RESET_B Core_Vdd IO_Vdd TIO00 TMS TDO TCK TDI 26 1.25 V Filter 3.3 V Figure A-2. 52-pin Vdd Connections DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 55 Watchdog Timer Timing A.2 A.2.1 Package Information 80-Pin Package . DSP56374 Data Sheet, Rev. 4.2 56 Freescale Semiconductor Watchdog Timer Timing DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 57 Watchdog Timer Timing DSP56374 Data Sheet, Rev. 4.2 58 Freescale Semiconductor Watchdog Timer Timing . DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 59 Watchdog Timer Timing A.2.2 52-Pin Package DSP56374 Data Sheet, Rev. 4.2 60 Freescale Semiconductor Watchdog Timer Timing DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 61 Watchdog Timer Timing DSP56374 Data Sheet, Rev. 4.2 62 Freescale Semiconductor Watchdog Timer Timing DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 63 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com DSP56374 Rev. 4.2, 1/2007 |
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